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FFT/IFFT Processor Design for 5G MIMO OFDM Systems

FFT/IFFT Processor Design for 5G MIMO OFDM Systems

Price : 13000

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Course Duration
Approx 9

Course Price
₹ 13000

Course Level
Beginner

Course Content

FFT/IFFT Processor Design for 5G MIMO OFDM Systems

Abstract

In this paper, a Fast Fourier Transform (FFT) or inverse FFT processor for Fifth-Generation (5G) Multiple Input Multiple Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) system’s baseband processor is implemented. The proposed 128-point FFT/IFFT processor employs mixed-radix (radix-2 and radix-2 3 )algorithm to reduce the number of complex multiplications. The pipelined FFT architecture with Multipath Delay Feedback (MDF) is chosen for FFT/IFFT processor implementation to have very high throughput rate and minimum power consumption. The resulting Mixed-Radix MDF (MRMDF) architecture provides a very high throughput rates for 1-8 simultaneous data sequences to meet new emerging standards of the MIMO-OFDM based systems. The hardware description is developed using Verilog and synthesized using Xilinx Virtex 5 FPGA family aiming to optimize the design in terms of area and speed at low frequency

 

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