Course Content

Implementation of Digital Logic Circuit in Artificial Neural Network with Floating Point Arithmetic using Verilog HDL

Abstract

This paper presents a hardware implementation of digital logic circuit i.e. half adder employing artificial neural networks. Numerous hardware implementations of ANNs already exist, the aim was to come up with an approach that would facilitate digital logic design implementations using floating point data for better precision described by Verilog HDL. The first challenge undertook was implementing the logic using floating point arithmetic which gives high precision at the cost of computation complexity and the second challenge was the hardware descriptive language used for implementation i.e. Verilog which has no prior available floating point arithmetic libraries unlike VHDL. This paper aims at implementing a generic hardware based ANN (MLPN) designed in Verilog HDL. This three-layer ANN is implemented completely with 32- bit single precision floating point arithmetic to assure flexibility and accuracy for its wide range of applications. The ANN enables reconfigurable perceptron per layer alongwith supervised learning through back propagation.