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VLSI implementation of AES Encryption/Decryption Algorithm

VLSI implementation of AES Encryption/Decryption Algorithm

Price : 13000

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Course Duration
Approx 11

Course Price
₹ 13000

Course Level
Beginner

Course Content

VLSI implementation of AES Encryption/Decryption Algorithm

Abstract

Encryption is the way to secure the personal data communication. It has wide applications in ATM, banking sector, defense sector, personal email system and so on. AES stands for Advanced Encryption Standard and it is very efficient algorithm available today in many systems. Depending upon the key length it will become more efficient. There are three key length options supported here, viz. 128,192 bit and 256 bit key length. Higher the key length more time is required to break the system or hack the system. 

AES IP core implements the 128-bit block-size NIST FIPS AES algorithm. The encryption core accepts a 128-bit plain text input data, and generates a corresponding 128-bit cipher text output data using a given 128 bit AES key. The decryption core provides the opposite function, generating plaintext from supplied cipher text, using the same AES key as was used for encryption. The algorithm is Complaint with the latest released Publication 197 from NIST.

 

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