FPGA Implementation of Digital Processing Blocks Using Optimal Resolution Multipliers
FPGA Implementation of Digital Processing Blocks Using Optimal Resolution Multipliers
Price : 14000
.svg)
FPGA Implementation of Digital Processing Blocks Using Optimal Resolution Multipliers
Abstract
The paper proposes an architecture of lossy multiplier for FPGA implementation. The proposed multiplier requires less logic resources but produces some error. This multiplier is being studied as a part of digital processing blocks: FIR-filters and FFT-processor. The results are verified using mathematical modeling tools and FPGA synthesis tools.