Course Content

Unified Hardware for High-Throughput AES-Based Authenticated Encryptions

Abstract

This brief presents an efficient unified hardware for up-to-date authenticated encryptions with associated data (AEADs). Although some major AEADs share several funda[1]mental components (e.g., advanced encryption standard (AES), block chaining, and XOR-Encryption-XOR (XEX) scheme), each AEAD is equipped with a unique mode of operation and/or sub[1]functions, which makes it difficult to integrate various AEADs in a hardware efficiently. The proposed hardware in this brief effi[1]ciently unifies the fundamental components to perform a set of AEADs with minimal area and power overheads. The proposed configurable datapath is adapted to a set of peripheral oper[1]ations (e.g., block chaining and XEX), dictated by the given AEAD algorithm. In this brief, we also demonstrate the valid[1]ity of the proposed hardware through an experimental design adapted to four AES-based AEADs. Consequently, we confirm that the proposed hardware can perform the four AEADs with quite smaller area than the sum of the each dedicated AEAD hardware, comparable throughput and power consumption. In addition, we confirmed that the proposed hardware is superior to software implementation on general-purpose processor in terms of both throughput and power consumption.